Efficient algorithm for polygon orthogonal partitioning in stranded-cell LEF generation flow

Digital standard cell library become an essential part of digital design flow and the success of integrated circuits; however, with the growing complexity in cell models, generation of a large digital cell library has increased the required processing jobs by 1000x in recent years. Recently users can find library files sized in gigabytes instead of megabytes, which requires a system that runs reliably and rapidly. Moreover, in nanometre technologies, design teams require more corners and complex models that can take 10 times longer than previous technologies. Place and route tools do not require full cell layout view; another abstract view needs to be generated for every standard cell, which is known by library exchange format (LEF). Correct Back-end library creation (LEF) is one of cornerstone for successful digital implementation. Place and route tools as well as layout verification tools rely on detailed LEF view information in digital libraries to accurately realize and verify the final design layout. In this paper, we are proposing new algorithms to partition any GDSII polygon into smaller rectangular polygons. Since current industrial tools do not support nonrectangular polygons, partitioning is one of the main steps in the GDSII to LEF conversion process. The new algorithm is polygon area-based rather than traditional techniques, which are relay on point-based algorithms. The new algorithm makes use of high capabilities of different layout tools in polygon processing to generate the LEF view from GDSII design. The proposed algorithm has been verified using large amount of digital cells from different technologies as 0.13um, 90nm and 45nm.