MCSMC: A new parallel Multi-level Cache Simulator For multi-core processors

Simulation is a widely accepted tool for evaluating any proposed cache system under different application and configuration scenarios because of the high degree of configurability of cache memory which requires extensive design space exploration and identification of performance bottlenecks in system understudy. In this paper we have presented a new multi-level cache Simulator, ´MCSMC´ (Multi-level Cache Simulator for Multi-Cores), developed for multi-core processors at NED University. It is a parallel trace-driven multi-level cache simulator based on module and layers approach. The developed simulator has been tested for upto 2048 cores and 10 cache levels with different cache performance parameters. It is coded in Visual C++ using OpenMP and Win32 process / thread libraries.