Variability-aware NoC geometry and topology scaling

In this paper we study the effects of geometry and topology scaling on electrical properties variations among NoC links designed to be identical. The modeled process systematic and random variations of current in CM interconnect, as well as delay variations in VM interconnect are calculated as interconnect, device and mesh size scale at 45 nm. Results show that device geometry scaling mainly affects the current variations. On the other hand, interconnect geometry scaling affects both current and delay variations. Scaling the mesh size will not affect random variations. On the other hand as the NoC mesh size scales from 4×4 to 16×16, the CM interconnect systematic current variations increases by 100%, while the VM systematic delay variations increases by 50% .