High performance CMOS buffer amplifier with offset cancellation

High performance CMOS buffer amplifier with offset cancellation is proposed. The new cell is based on negative feedback technique; therefore it improves the proposed cell performance. The employed feedback enhances the overall transconductance while minimizing the loading effect on the driving stage. The proposed cell can be used as a very high bandwidth buffer with resistive and capacitive load. The offset cancellation technique is achieved using level shifter based on current process. The proposed approach can be easily using for offset cancellation of the main analog blocks, such as operational amplifier, Variable Gain Amplifier (VGA), ....etc. The proposed circuit is designed and simulated using 0.13μm CMOS process from IBM. The simulation results show bandwidth of 1.6GHz for a 3pF capacitor and 50Ω resistor. The consumed power was 4.5mW which is reasonable for such large load comparing to a conventional source follower buffer and other approaches.