Cost effective application of advanced computational lithography techniques using flexible mask optimization

The 2x nm technology node, with its very low k₁ values using immersion lithography is made possible by using advanced computational lithography. Computational techniques such as accounting for 3D effects (including mask topography, wafer sub-layers and resist profiles) in OPC models, the use of model based assist feature placements and the application of process window based OPC solvers have become essential for addressing critical patterning issues. Although these methods can be complex and computationally expensive there is a cost effective application using a framework known as flexible mask optimization or FMO [1,2]. In this study, we show a successful demonstration of such an approach for an advanced technology node using FMO. In the typical OPC development period, various issues may be found which require additional fine tuning. However, each adjustment of the OPC recipe can have unintended consequences in other parts of the chip. This iterative nature of tuning to correct one design area, only to have to then correct a new design area as a consequence, can be endless and very costly. With this FMO flow, critical patterns were identified, classified and corrected using advanced techniques only in localized areas. FMO uses a model based method to ensure defect free boundaries and guarantees that no hotspots are generated as a result of using multiple correction methods on the same layout. The key advantage for FMO is enabling the application of advanced OPC techniques only where necessary. This study demonstrates flows using various case studies on different types of defects and correction methods. The data shows that by using the FMO approach the critical patterns were corrected with defect free boundaries. Mask rule checks (MRC) for main patterns and SRAF are shown clean for all cases. The cost benef