DocumentCode :
614940
Title :
Mechanical characteristics of thin dies/wafers in three-dimensional large-scale integrated systems
Author :
Murugesan, Mariappan ; Fukushima, Tetsuya ; Bea, J.C. ; Lee, Kuan Waey ; Koyanagi, Mitsumasa ; Tanaka, T.
Author_Institution :
New Ind. Creation Hatchery Centre, Tohoku Univ., Sendai, Japan
fYear :
2013
fDate :
14-16 May 2013
Firstpage :
66
Lastpage :
69
Abstract :
Ultra-thin silicon dies/wafers with thickness less than 30 μm are profoundly used in the 3D-integration (vertical stacking of functional chips) and in the optoelectronics, in order to reduce the interconnect length and the resistive-capacitive delay. However, to improve the quality and fabrication yield of the three-dimensional large-scale integration (3D-LSI) process, it is important to have very good mechanical properties of such ultra-thin dies. Mechanical properties of the ultra-thin dies such as Young modulus (using nano-indenter), residual stress (by laser micro-Raman spectroscopy), and also the crystal orientation (by using electron back-scatter diffraction) were investigated with respect to different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc), for various wafer thicknesses (10 μm, 30 μm, 50 μm, 100 μm, 200 μm) and for the different kinds of the wafer (P/P+, P/P-, and wafer with internal gettering (IG) layer). The chemically-mechanically polished ultra-thin dies/wafers were found to be extraordinarily good in terms of mechanical strength as well as residual stress as compared to the ultra-thin dies/wafers fabricated by all other die thinning procedures.
Keywords :
integrated circuit interconnections; integrated circuit manufacture; integrated optoelectronics; large scale integration; mechanical strength; quality control; three-dimensional integrated circuits; 3D integration; 3D-LSI process; fabrication yield; interconnect length; mechanical characteristics; mechanical properties; mechanical strength; optoelectronics; quality; resistive-capacitive delay; three-dimensional large-scale integrated systems; ultra-thin silicon dies/wafers; Force; Large scale integration; Silicon; Stress; Young´s modulus; Hardness; Young modulus; nano-indentation; stress-relief method; ultra-thin silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location :
Saratoga Springs, NY
ISSN :
1078-8743
Print_ISBN :
978-1-4673-5006-8
Type :
conf
DOI :
10.1109/ASMC.2013.6552777
Filename :
6552777
Link To Document :
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