DocumentCode
614962
Title
Die level defects detection in semiconductor units
Author
Said, Ahmad Fahmi ; Patel, Nital S.
Author_Institution
ATTD Autom. Pathfinding, Intel Corp., Chandler, AZ, USA
fYear
2013
fDate
14-16 May 2013
Firstpage
130
Lastpage
133
Abstract
The assembly test process has many steps where defects can be created at any time during different stages. Detecting defects at early stages is very crucial and saves a lot of cost and time by isolating the defective parts from further processing. Detecting defects on the die area of the semiconductor units is a challenging procedure due to the fact that die´s defects exhibits large variations in intensity and shape. The existing manual and automated inspection approaches still produce high rate of under-rejection and over-rejection which impacts the yield and adds significant cost to the inspected unit. A robust die level defect detection procedure is presented in this paper in order to come up with a solution that is cheaper, easier to sustain, and that would automatically inspect each unit for defects providing for efficient baseline characterization and rapid excursion detection. The proposed method gives a higher detection rate of die level defects with under-rejecting and over-rejection rates within the acceptable criteria.
Keywords
inspection; integrated circuit testing; integrated circuit yield; assembly test process; automated inspection; baseline characterization; defective parts; die level defects detection; integrated circuit yield; rapid excursion detection; semiconductor units; Cameras; Feature extraction; Histograms; Image segmentation; Inspection; Robustness; Shape; Segmentation; defect detection; die level defects; feature analysis; shape analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location
Saratoga Springs, NY
ISSN
1078-8743
Print_ISBN
978-1-4673-5006-8
Type
conf
DOI
10.1109/ASMC.2013.6552800
Filename
6552800
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