New test bench for evaluation of IEEE 802.15.4 CSS timestamping capabilities

The paper deals with a new test bench for the assessment of time-related performance of wireless systems implementing the IEEE 802.15.4 with the Chirp Spread Spectrum (CSS) physical layer. The test bench has been designed in order to clearly evaluate the timestamping capabilities of an FPGA-based implementation of the IEEE 802.15.4 CSS. The key features are the full bandwidth capability and the extreme flexibility thanks to the FPGA hardware which is completely programmable. The Synchronous Ethernet embedded in the test nodes guarantees the easy synchronization of device clocks through a wired backbone, which allows for estimation of the peak performance of the system under test. A case study is presented regarding a basic implementation of the IEEE 802.15.4 CSS; under the experimental conditions, the mean timestamping error of the evaluated system is less than 200 ps.