Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS

A 16-b, 1MSps successive approximation ADC in 180nm CMOS uses the ”split ADC” architecture to enable continuous, all-digital, background self-calibration of ADC linearity. Convergence of calibration parameters to noise-limited accuracy is demonstrated with an adaptation time constant less than 300ms. In the capacitive DAC, a novel segmentation and shuffling approach is used to mitigate requirements on input signal activity; calibration is possible even in the presence of DC input signals.