Title :
High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style
Author :
Midhun, C.K. ; Joy, Joshua ; Kavitha, R.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Tiruchirappalli, India
Abstract :
This brief proposes a new type of high throughput asynchronous pipeline structure called self-precharging (SP) pipeline. The proposed SP pipeline targets dynamic linear datapaths for fine grain and gate level pipelining. The novel SP protocol and modified structure enables SP pipeline to deliver multi gigahertz throughput without degrading the per-stage forward latency of the pipeline. An asymmetric C (aC) element is used to combine the two control signals, which are used to evaluate and precharge a stage. Because of the aC element, the pipeline is able to remove one of the important timing constraints present in lookahead pipelines (LP). Since the SP signal is coming from the same stage without altering the functionality of the signal, the wiring load of handshaking signals between two stages is maintained minimum. The pipeline is implemented in 90 nm UMC technology and it offers (2.227 giga data items/s) more than twice the throughput of Williams´ PS0 and more than 20% improvement over the best lookahead dual rail pipeline (LP2/1). The area and power consumption of the proposed pipeline are comparable with the state-of-the-art asynchronous pipeline topologies.
Keywords :
asynchronous circuits; logic design; asymmetric C element; dual-rail logic; dynamic logic; fine grain pipelining; gate level pipelining; handshaking signals; high-speed dynamic asynchronous pipeline; lookahead dual rail pipeline; self-precharging pipeline; size 90 nm; Delays; Detectors; Pipeline processing; Pipelines; Protocols; Rails; Throughput; Asynchronous pipeline; dual-rail logic; dynamic logic; fine-grain pipelining; fine-grain pipelining.;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2282834