A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function

A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast settling without exhibiting overshoots. While most previously reported peaking-free PLLs require additional circuit components which may adversely affect clock jitter or increase hardware complexity, the presented PLL requires only a new type of digital loop filter. The analysis on the loop dynamics and design of the optimal loop filter are presented. As for the implementation, a low-power linear time-to-digital converter (TDC) is realized with a set of three binary phase-frequency detectors whose triggering clocks are dithered using a delta-sigma modulator and phase interpolators. A digitally controlled oscillator (DCO) is implemented as a transformer-tuned LC oscillator whose frequency is set by a ratio between two digitally controlled currents. The digital PLL prototype, fabricated in a 65 nm CMOS, demonstrates 1.2 ps rms integrated jitter at 9.2 GHz and 1.58 μs settling time with 700 kHz bandwidth while dissipating 63.9 mW at a 1.2 V nominal supply.