Implementation of CMOS charge sharing dynamic latch comparator in 130nm and 90nm technologies

Author

Kapadia, Dhanisha N. ; Gandhi, Priyesh P.

Author_Institution

L.C. Inst. of Technol., Bhandu, India

fYear

2013

fDate

11-12 April 2013

Firstpage

16

Lastpage

20

Abstract

This paper proposes a CMOS charge sharing dynamic latch comparator along with the Buffer stage in 130nm and 90nm technologies. The supply voltage for this comparator is 1.3v and 0.9v for 130nm and 90nm respectively. Various analysis of different characteristics of the comparator such as offset, ICMR, propagation delay, power dissipation has been carried out in both the technologies and the result has been compared for both the technologies. The simulation results shows that speed of 1.33GHz and 0.47GHz was achieved with the power dissipation of 4.89mW and 167.32mW in 90nm and 130nm technologies respectively.

Keywords

CMOS logic circuits; buffer circuits; comparators (circuits); flip-flops; CMOS charge sharing dynamic latch comparator; ICMR; buffer stage; frequency 0.47 GHz; frequency 1.33 GHz; power 167.32 mW; power 4.89 mW; power dissipation; propagation delay; size 130 nm; size 90 nm; supply voltage; voltage 0.9 V; voltage 1.3 V; CMOS integrated circuits; Communications technology; Conferences; Latches; MOSFET; Propagation delay; Buffer stage; charge sharing network; latch comparator;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558054

Filename

6558054