Peak noise and noise width modelling for RLC global interconnects in deep submicron VLSI circuits

This paper presents a new method to estimate the crosstalk noise for on-chip VLSI RLC global interconnects using 2-π model. Distributed RLC on-chip global interconnects can be modelled for an above low frequency operation with sufficient accuracy and better result. To calculate this crosstalk noise we apply the unit step input to the aggressor network side which is adjacent to the victim network. This proposed model presents the noise voltage waveform by using 2-π model. This noise voltage generated at the output of the victim network. This paper also gives the idea of peak crosstalk noise amplitude and noise width for on-chip global RLC VLSI interconnects. Some mathematical technique are using for calculating the peak noise amplitude and noise width for RLC interconnect. The dominant pole method is best one because this method reduces the complexity of the transfer function of complex electrical network. So, the finally we get average error of less than 6% when compared to that of the SPICE simulation. So, this is the better technique to use than the SPICE result.