Used self-controllable voltage level technique to reduce leakage current in DRAM 4×4 in VLSI

As the technology improved to support very large chip sizes, system designers were faced with power consumption problem and leakage current problem. CMOS technology has increased in level of importance to the point where it now clearly holds center stage as the dominant VLSI technology In this research paper shows the implementation of a DRAM 4×4 (dynamic random access memory) with self controllable voltage level (SVL) technique. SVL technique is leakage current reduction technique. Simulation is done by using a microwind 3.1 and DSCH 2. By using a SVL technique in DRAM 4×4, 37% of leakage current is reduced.