Through silicon via admittance field solver with system level capacity: Application

Author

Kourkoulos, V. ; Suaya, Roberto

Author_Institution

Design to Silicon, Mentor Graphics, Grenoble, France

fYear

2013

fDate

12-15 May 2013

Firstpage

1

Lastpage

4

Abstract

A new methodology has been proposed for the accurate and efficient admittance (capacitance/conductance) characterization of three dimensional (3D) interconnects. Its accuracy lies at the use of the method of moments for the characterization of the unknown quantities. The compact representation of unknowns and the derivation of closed form expressions for all the coefficients of the method of moments linear system lead to a very computationally efficient implementation. In this paper, we provide experimental support to the previous claims for the study of the capacitance/conductance of 3D interconnects. Our examples dwell with sensitivity to frequency, depletion region effects, and placement.

Keywords

integrated circuit interconnections; method of moments; three-dimensional integrated circuits; 3D interconnects; MoM linear system; admittance characterization; capacitance-conductance characterization; depletion region effects; method of moments; system level capacity; three-dimensional interconnects; through silicon via admittance field solver; Accuracy; Admittance; Capacitance; Conductors; Silicon; Substrates; Through-silicon vias; Admittance extraction; interconnects; method of moments; substrate effects; through silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal and Power Integrity (SPI), 2013 17th IEEE Workshop on

Conference_Location

Paris

Print_ISBN

978-1-4673-5678-7

Type

conf

DOI

10.1109/SaPIW.2013.6558314

Filename

6558314