High performance fine grained dynamic power estimation technique for multilevel caches using architectural simulator - Imperas

This paper presents a novel dynamic power estimation technique for differently configured multilevel caches at very fine granular level. High performance power extraction tool has been developed to monitor the dynamic power dissipation for modern high speed multilevel caches of microprocessor. The microprocessor furnished with multilevel caches is assembled as a virtual platform using different libraries of Imperas Open Virtual Platform Technology. This methodology involves extraction of granular level micro operations exercised by multilevel caches using instruction accurate Just-In-Time Binary Interception Technology. A power extraction tool based on binary interception library is created to extract hit and miss rates of instruction as well as data caches and other performance parameters to estimate dynamic power. Furthermore, the performance of our power profiling tool has been compared with already proposed techniques. The developed method has resulted in reduced simulation time complexity, space complexity and development effort.