Power gating applied to MP-SoCs for standby-mode power management

Complex SoCs from servers to intelligent sensors are increasingly built up from heterogeneous IP cores and subsystems. Accelerator blocks or additional processor cores support both general purpose and graphics optimized processing in mobile SoCs, but the number of cores that may be simultaneously active is typically restricted for both battery life and thermal package limits. Power gating is the primary approach to cutting the leakage power for inactive blocks, while state retention and standby voltage scaling can be valuable enhancements for improving energy and latency costs for such leakage mitigation schemes. This paper describes work on techniques that look promising to build on current multivoltage EDA tools and power intent, without the costs of resorting to full-custom design techniques.