DocumentCode :
621270
Title :
Improved deep trench isolation breakdown voltage for SmartMOS
Author :
Thuy Dao ; Roggenbauer, Todd ; Boyd, G.
Author_Institution :
Freescale Semicond., Austin, TX, USA
fYear :
2013
fDate :
29-31 May 2013
Firstpage :
101
Lastpage :
104
Abstract :
To achieve higher voltage analog and power devices, the deep trench isolation breakdown voltage must withstand the higher operating voltages. Optimization of deep trench etch to produce a straighter etch profile enable a void free poly filled trench, adding HF clean improve liner oxide film quality and changing liner oxidation process change the fill profile enable the oxide liner thickness to increase result in increase in the deep trench isolation (DTI) breakdown voltage.
Keywords :
MOS integrated circuits; elemental semiconductors; isolation technology; power integrated circuits; power semiconductor devices; semiconductor device breakdown; silicon-on-insulator; DTI breakdown voltage; HF clean; SmartMOS; deep trench etch optimization; improved deep trench isolation breakdown voltage; liner oxidation process; liner oxide film quality; oxide liner thickness; power device; void-free poly-filled trench; voltage analog device; Breakdown voltage; Diffusion tensor imaging; Films; Hafnium; Layout; Optimization; Oxidation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
Type :
conf
DOI :
10.1109/ICICDT.2013.6563313
Filename :
6563313
Link To Document :
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