• DocumentCode
    623170
  • Title

    Research and implementation on multi-DDS technology in high performance digital up-conversion

  • Author

    Ji Liao ; Xiaoming Ye ; Xiaoguang Hu ; Dan Sun

  • Author_Institution
    Sch. of Autom. Sci. & Electr. Eng., Beihang Univ., Beijing, China
  • fYear
    2013
  • fDate
    19-21 June 2013
  • Firstpage
    178
  • Lastpage
    183
  • Abstract
    Digital Up-conversion is the core technology in digital radar transmitter. With the demand on the performance and functionality of digital radar transmitter increases highly, it is particularly necessary to develop high-efficient up-conversion technology. Multi-DDS algorithm proposed in this paper combines parallel processing thinking with theory of Direct Digital Synthesizer and utilizes the simultaneous operation of multiple traditional DDS unit. Meanwhile, it takes advantage of rich logic resources in FPGA to achieve IF signal with large bandwidth, high sampling rate on a low clock hardware platform.
  • Keywords
    direct digital synthesis; radar transmitters; FPGA; IF signal; clock hardware platform; core technology; digital radar transmitter; direct digital synthesizer; high efficient up conversion technology; high performance digital up conversion; multiDDS algorithm; multiDDS technology; parallel processing; Bandwidth; Clocks; Field programmable gate arrays; Frequency control; Hardware; Radar; Table lookup; Digital Up-conversion; Multi-DDS algorithm; high-efficient; parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Industrial Electronics and Applications (ICIEA), 2013 8th IEEE Conference on
  • Conference_Location
    Melbourne, VIC
  • Print_ISBN
    978-1-4673-6320-4
  • Type

    conf

  • DOI
    10.1109/ICIEA.2013.6566361
  • Filename
    6566361