DocumentCode :
623503
Title :
GPU design in a power-limited era
Author :
Khailany, Brucek
Author_Institution :
NVIDIA Corp., Santa Clara, CA, USA
fYear :
2013
fDate :
2-3 June 2013
Firstpage :
68
Lastpage :
68
Abstract :
As we enter this era of power-limited computing with GPUs playing a leading role in parallel processor architecture, interesting design challenges need to be faced and new tradeoffs need to be considered. For example, aggressively reducing operating voltage closer to threshold has been proposed as one way to overcome power limitations. However, this approach can introduce complications related to variation-related effects and yield issues, power delivery losses at low voltage, and significant degradations in performance per mm2. Alternative approaches to improving power efficiency include micro-architectural techniques for eliminating wasteful energy in data and instruction operand delivery on-chip, particularly in the presence of data parallelism. Many of these and other techniques will play a key part in continuing to scale GPU performance in the presence of power dissipation limitations in future technologies.
Keywords :
graphics processing units; integrated circuit design; integrated circuit yield; parallel architectures; GPU design; GPU performance; data parallelism; design challenge; graphics processing units; microarchitectural technique; operating voltage reduction; parallel processor architecture; power delivery loss; power dissipation limitation; power efficiency; power-limited computing; power-limited era; variation-related effects; wasteful energy; yield issues; Bandwidth; Computer architecture; Graphics processing units; Mobile handsets; Parallel processing; Performance evaluation; Power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Systems Education (MSE), 2013 IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4799-0139-5
Type :
conf
DOI :
10.1109/MSE.2013.6566707
Filename :
6566707
Link To Document :
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