• DocumentCode
    6242
  • Title

    Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary

  • Author

    Wang, Lisa Ling ; Kuo, J.B. ; Shengdong Zhang

  • Author_Institution
    Sch. of Comput. & Inf. Eng., Peking Univ., Shenzhen, China
  • Volume
    60
  • Issue
    3
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    1122
  • Lastpage
    1127
  • Abstract
    This paper presents an analytical hot-carrier effect model for n-channel poly-Si thin-film transistors biased in strong inversion based on degradation of tail states at grain boundary near drain after stress. Via a stress-time-dependent tail state model, the degradation of tail state distribution and drain current after stress could be predicted as verified by the experiment data. Based on this model, both the tail state density and the characteristic decay energy of the tail state distribution in the damaged region increase with the stress time, which determine the degradation of the drain current.
  • Keywords
    elemental semiconductors; grain boundaries; semiconductor device models; silicon; thin film transistors; Si; analytical drain current model; analytical hot-carrier effect model; characteristic decay energy; grain boundary; n-channel poly-silicon thin-film transistors; stress-time-dependent tail state model; tail state degradation; tail state density; tail state distribution degradation; Data models; Degradation; Electron traps; Logic gates; Stress; Thin film transistors; Video recording; Degradation; hot carriers; poly-Si thin-film transistors (TFTs); reliability;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2012.2236332
  • Filename
    6409443