Automatic Generation of Architecture Model for Reconfigurable Build Tools

The wide spread of application specific processors like network or communication processors generated the need of optimizing retargetable software development tools such as compiler, linker, debugger, assembler and simulator. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). The ADL should be both simple and covering. The simplicity is translated into less effort to describe an architecture and the coverage means that the description provides enough information to the development tools. In this paper we focus on the challenges faced trying to accomplish these two main characteristics taking into account different classes of processors DSP, MCU, MPU. We propose a flat description generated from a sketch of the architecture. We show that the flat description is reducing the compilation time especially in optimizing parts (code generation, register allocation, encoding, instruction scheduling).