Variability-aware and fault-tolerant self-adaptive applications for many-core chips

Author

Bizot, Gilles ; Chaix, Fabien ; Zergainoh, Nacer-Eddine ; Nicolaidis, Michael

Author_Institution

TIMA Lab., ARIS Team, France

fYear

2013

fDate

27-30 May 2013

Firstpage

1

Lastpage

1

Abstract

The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip subject to intra-die variability.

Keywords

failure analysis; system-on-chip; SoC; computing cores; fault-tolerant self-adaptive applications; high-level method; intra-die variability; many-cores processor system on chip; parallel application; variability-aware applications; Circuit faults; Computational modeling; Europe; Fault tolerance; Fault tolerant systems; Program processors; System-on-chip; Distributed applications; Energy-aware systems; Many-cores Processor; Multiprocessor Systems; Self-Adaptive Self-Mapping; System on Chip; Variability-Aware;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2013 18th IEEE European

Conference_Location

Avignon

Print_ISBN

978-1-4673-6376-1

Type

conf

DOI

10.1109/ETS.2013.6569379

Filename

6569379