Test Generation for RTES from SysML Models: Context, Motivations and Research Proposal

This paper presents the context, motivations and perspectives of my PhD research about model-based testing for real-time and embedded systems using SysML. This work is based on an existing model-based approach which has been proposed during the VETESS project. This approach aims to generate tests for embedded systems. In this paper, we identify areas of improvement, which permit us to evolve the initial approach by taking into account real-time aspects. This will contribute to an automated Model-Based Testing tool-chain for real-time and embedded systems.