DocumentCode
625772
Title
Design of a (255, 239) Reed-Solomon decoder using a simplified step-by-step algorithm
Author
Yu-Shan Su ; Chu Yu ; Bor-Shing Lin ; Po-Hsun Cheng ; Sao-Jie Chen
Author_Institution
Dept. of Electron. Eng., Nat. ILan Univ., Ilan, Taiwan
fYear
2013
fDate
3-6 June 2013
Firstpage
247
Lastpage
248
Abstract
This paper presents the design of a new (255, 239) Reed-Solomon (RS) decoder using a simplified step-by-step algorithm. For calculating the syndrome determinant in the RS decoder, the proposed architecture performs Gauss elimination on a 1-D systolic array that has lower hardware complexity and is more suited to be used on a higher-dimension matrix with the step-by-step algorithm. The proposed architecture, designed in 0.18 μm CMOS technology, has approximately 25K gates, and consumes approximately 40 mW at 250 MHz.
Keywords
CMOS logic circuits; Gaussian processes; Reed-Solomon codes; decoding; systolic arrays; (255, 239) RS decoder; (255, 239) Reed-Solomon decoder; 1D systolic array; CMOS technology; Gauss elimination; frequency 250 MHz; hardware complexity; higher-dimension matrix; power 40 mW; size 0.18 mum; Algorithm design and analysis; Arrays; Calculators; Complexity theory; Decoding; Educational institutions;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ISCE), 2013 IEEE 17th International Symposium on
Conference_Location
Hsinchu
ISSN
0747-668X
Print_ISBN
978-1-4673-6198-9
Type
conf
DOI
10.1109/ISCE.2013.6570209
Filename
6570209
Link To Document