Title :
A 0.38 mm2, 10mhz-6.6 GHz quadrature frequency synthesizer using fractional-N injection-locked technique
Author :
Wei Deng ; Musa, Afiqah ; Okada, Kenichi ; Matsuzawa, Akira
Author_Institution :
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
Abstract :
This paper presents an area- and power-efficient delta-sigma frequency synthesizer with a quadrature phase output using a fractional-N injection-locking technique. A digital calibration scheme is proposed to compensate for the PVT variations. Implemented in a 65nm CMOS process, this work demonstrates 10 MHz to 6.6 GHz continuous frequency coverage with quadrature output, while only occupies a small area of 0.38 mm2 and consumes 16-26 mW depending on output frequency. The normalized phase noise achieves -135.3 dBc/Hz at 3 MHz offset, and -95.1 dBc/Hz in-band phase noise at 10 kHz offset, from a 1.7GHz carrier frequency.
Keywords :
CMOS integrated circuits; calibration; delta-sigma modulation; frequency synthesizers; phase noise; software radio; CMOS process; PVT variations; delta-sigma frequency synthesizer; digital calibration; fractional-N injection-locked technique; frequency 10 MHz to 6.6 GHz; normalized phase noise; power 16 mW to 26 mW; quadrature frequency synthesizer; quadrature phase output; size 65 nm;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/ASSCC.2012.6570787
