An inductive-coupling interconnected application-specific 3D NoC design

To deal with interconnect delay problem, through-silicon-via (TSV) based 3D interconnect is widely used. However, TSV-interconnected 3D chips face problems such as high cost, low yield and large power dissipation. In this paper, we propose a wireless 3D on-chip-network architecture for application-specific SoC design, using inductive-coupling interconnect instead of TSV for inter-layer communication, which cuts down manufacture cost, improves interconnect performance, reduces power consumption and provides larger design space. The key to this design is allocating wireless links in the 3D on-chip network effectively while maintaining signal integrity. We develop a design flow which can fully exploit the design space brought by wireless links and provide flexible tradeoff for user´s choice. Experimental results show that our architecture brings great improvement on both performance and power consumption.