A process-variation compensation scheme to operate CMOS digital logic cells in deep sub-threshold region at 80mV

Author

Kappel, R. ; Auer, Mario ; Pribyl, W. ; Hofer, G. ; Holweg, Gerald

Author_Institution

Inst. of Electron., Graz Univ. of Technol., Graz, Austria

fYear

2013

fDate

19-23 May 2013

Firstpage

562

Lastpage

565

Abstract

In this paper a simple technique to use standard digital CMOS logic cells from 80mV to 1.2V is presented. By applying a compensation network process-related variations of the logic´s switching threshold can be reduced by 89% for a given supply voltage. Therefore post-fabrication process steps can be avoided. The principle is introduced by a simple inverter gate and expanded to more complex NAND, NOR and Flip-Flop cells. A test chip has been fabricated in a 130nm process proving the functionality of the proposed digital cells.

Keywords

CMOS logic circuits; NAND circuits; NOR circuits; compensation; flip-flops; logic testing; NAND cell; NOR cell; deep subthreshold region; flip-flop cell; inverter gate; logic test chip; post-fabrication process; process-variation compensation scheme; size 130 nm; standard digital CMOS digital logic cell; switching threshold; voltage 80 mV to 1.2 V; CMOS integrated circuits; Inverters; Logic gates; Standards; Switches; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6571904

Filename

6571904