A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations

We investigate the prospect of low-jitter wide frequency range high-speed clocking implementation. A novel architecture features multi-LCVCO with mitigation of dormant VCO leakage current and capacitive modulation is proposed. The new scheme decouples the typical trade-offs between tuning-range, achievable speed and jitter-performances. It enables high frequency low jitter PLL design with sizable tuning range in nowadays highly leaky standard CMOS. A novel self calibration method is presented to seamlessly activate a proper VCO with a proper switched-tuning band to bias the PLL in its optimal operating point. Hence, design requirements for critical circuits including the VCO, the first divide-by-2 and the loop-filter are relaxed. The proposed scheme was implemented and validated in silicon.