Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

This work investigates the effects of process variability on the dynamic stability of a 6-Transistor Static Random Access Memory bitcell manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) technology node. The study is carried out for two different well architectures: single-well (peculiar to UTBB-FDSOI) and dual-well (like in standard CMOS), through Most-Probable Failure Point tracking methodology coupled with Importance Sampling. Different failure mechanisms appearing under different operating conditions are discussed. We show that the Read-After-Write failure criterion based on multiple Word-Line pulses is the most accurate way to evaluate bitcell failure rate and thus its yield under realistic dynamic conditions. The methodology exposed in this work is applied to demonstrate the superior properties of the single-well architecture.