Design and verification of an all-digital on-chip process variation sensor

This paper presents a process variation sensing circuit technique for maintaining the performance benefit of CMOS digital circuits and reducing variations in delay and robustness. The new process sensor consists of two inverter chains with different loading capacitances and a time-to-digital converter (TDC) that detects delay variations between the inverter chains. Results based on the measured TDC data are used to adjust the supply voltages of systems to optimal values. This technique considerably saves power in digital circuits and increases yield in high performance bins. In order to verify the operation and performance of the novel sensor, an all-digital delay-locked-loop (DLL) was designed and its jitter was measured. The circuits, which were fabricated with a 0.13um CMOS process, showed the 20% improved jitter variations compared with a conventional DLL without process compensation.