A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM

Author

Kyoungtae Lee ; Yeonam Yoon ; Nan Sun

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA

fYear

2013

fDate

19-23 May 2013

Firstpage

2006

Lastpage

2009

Abstract

This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.

Keywords

CMOS integrated circuits; SPICE; analogue-digital conversion; closed loop systems; digital elevation models; feedback; operational amplifiers; power supplies to apparatus; voltage-controlled oscillators; CMOS technology; DEM capability; SNDR ΔΣ ADC; SNDR degradation; SPICE simulation; VCO-based ADC; VCO-based integrators; feedback DAC; first-order close-loop VCO-based ΔΣ ADC; frequency 10 MHz; operational amplifier; power 5.6 mW; power hungry; power supply; scaling unfriendly; signal bandwidth; size 0.13 mum; Bandwidth; CMOS integrated circuits; CMOS technology; Degradation; Noise; SPICE; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572264

Filename

6572264