Statistical Electromigration analysis of a chip with the consideration of a within-die temperature map

In this paper, we present a new approach which uses statistical methods to analyze the Electromigration (EM) reliability of a chip. This new approach utilizes statistical nature of EM failure distribution to assess overall EM risk and applies a within-die temperature map on a chip level design of multiple metal and via layers. The new proposed method provides a more optimistic EM violation estimation result when compared with results using traditional method.