• DocumentCode
    627162
  • Title

    A 2μW digital baseband core for wireless Micro-Neural-Interface in 0.18μm CMOS

  • Author

    Ran Liao ; Hutchens, Chriswell ; Rennaker, Robert L.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA
  • fYear
    2013
  • fDate
    19-23 May 2013
  • Firstpage
    3008
  • Lastpage
    3011
  • Abstract
    This paper presents the design of a low power digital baseband core with a custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) system on a chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of multiple sensors, is designed to control the operation and the interface with the whole MNI SoC based on received downlink commands and store/dump targeted neural data uplink in an energy efficient way. Robust low power cell library and on-chip SRAM memory are specially designed to achieve robust low-voltage operation with targeted timing constraints. The average measured power is 2μW at 1.28MHz system clock under 450mV power supply and a communication data rate of 640Kbps.
  • Keywords
    CMOS integrated circuits; low-power electronics; protocols; sensor fusion; system-on-chip; CMOS; custom-tailored protocol; digital baseband core; energy efficient; frequency 1.28 MHz; multiple sensors; neural data uplink; power 2 muW; size 0.18 mum; system on a chip; voltage 450 mV; wireless microneural-interface; Baseband; Clocks; Libraries; Power supplies; Protocols; Random access memory; Wireless sensor networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
  • Conference_Location
    Beijing
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-5760-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2013.6572512
  • Filename
    6572512