The divided flash memory device for implementing neurons and neural networks

Neural networks have been of interest for long, but have been hard to implement in practice, because of excessive complexity and training required. Neural networks have been proposed with hardware, such as with FPGAs and VLSI. This paper proposes implementing neurons and neural networks with MOS Flash memory technology. The floating gate of the flash memory can store a charge for years, influencing the conductivity of the channel. It is proposed that the gates be divided into a number of control gate-floating gate pairs. Each gate pair will behave mostly independently, with the charged floating gate acting as a weighting on the input. The multiple floating and control gates may replicate the weighting and summation of inputs to dendrons, and their output to an axon. The voltage of the floating gate may be the “training” required in neural networks, and may be set by a method such as backpropagation. The resulting conductivity of the channel will be a non-linear combination of the inputs, very similar to the functioning of a neuron. The proposed devices may be placed in parallel for a different set of behaviors. The non-linearities of the divided Flash memory will have similarities and differences with the nonlinearities of a neuron. The non-linearities of the divided Flash memory may be manipulated through design to give optimized results for a neural network. Billions of divided Flash memory devices, and artificial neurons may be implemented in a single chip.