Analog encoded neural network for power management in MPSoC

Author

Larras, Benoit ; Boguslawski, Bartosz ; Lahuec, Cyril ; Arzel, Matthieu ; Seguin, Fabrice ; Heitzmann, Frederic

Author_Institution

Electron. Dept., TELECOM Bretagne, Brest, France

fYear

2013

fDate

16-19 June 2013

Firstpage

1

Lastpage

4

Abstract

Encoded neural networks mix the principles of associative memories and error-correcting decoders. This paper introduces an analog implementation of this new type of network to manage the power distribution in Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1V supply ST CMOS 65nm process, with a low complexity and low power consumption (less than 1% of the MPSoC power). Compared to a digital counterpart based on game theory, this analog solution consumes 6800 times less energy and reacts 4500 times faster. Thus, this analog circuit allows to fully exploiting DVFS circuits switching capabilities to continuously adapt the power distribution of an MPSoC.

Keywords

content-addressable storage; decoding; error detection codes; low-power electronics; microprocessor chips; neural nets; system-on-chip; DVFS circuit switching capability; MPSoC; ST CMOS; analog circuit; associative memory; error-correcting decoder; multiprocessor system-on-chip; power consumption; power distribution management; power management; size 65 nm; voltage 1 V; Clocks; Complexity theory; Energy consumption; Integrated circuit interconnections; Neural networks; Switching circuits; Time factors;

fLanguage

English

Publisher

ieee

Conference_Titel

New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International

Conference_Location

Paris

Print_ISBN

978-1-4799-0618-5

Type

conf

DOI

10.1109/NEWCAS.2013.6573589

Filename

6573589