Low power magnetic flip-flop based on checkpointing and self-enable mechanism

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep submicron CMOS technology. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Torque Transfer MRAM (STT-MRAM) is considered the most promising NVM technology to address this issue thanks to its fast speed, low power, and infinite endurance. In this paper, we present a new design of magnetic flip-flop (MFF) based on STT-MRAM. By integrating multi-context data checkpointing and self-enable switching mechanisms, its overall power can be lowered further than conventional structures. We performed hybrid simulations to validate its functional behaviors and evaluate its performance by using an accurate STT-MRAM spice model and an industrial CMOS 40 nm design kit.