• DocumentCode
    628240
  • Title

    Evaluating Xilinx SEU Controller Macro for fault injection

  • Author

    Nunes, Jose Luis ; Cunha, Joao Carlos ; Barbosa, Ramiro ; Zenha-Rela, Mario

  • Author_Institution
    CISUC, Polytech. Inst. of Coimbra, Coimbra, Portugal
  • fYear
    2013
  • fDate
    24-27 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This paper presents a preliminary evaluation of the SEU Controller Macro, a VHDL component developed by Xilinx for the detection and recovery of single event upsets, as a building block of an FPGA fault-injector. We found that this SEU Controller Macro is extremely effective for injecting faults into the FPGA configuration memory, as single and double bit-flips, with precise location, virtually no intrusiveness, and coarse timing accuracy. We present some clues on how to extend its functionalities to build a fully-fledge FPGA fault injector.
  • Keywords
    fault tolerant computing; field programmable gate arrays; hardware description languages; FPGA configuration memory; VHDL component; Xilinx SEU controller macro evaluation; double bit-flips; fault injection; field programmable gate arrays; single bit-flips; single event upset detection; single event upset recovery; Accuracy; Circuit faults; Embedded systems; Field programmable gate arrays; Single event upsets; System analysis and design; FPGA; SEU; embedded systems; fault injection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Systems and Networks (DSN), 2013 43rd Annual IEEE/IFIP International Conference on
  • Conference_Location
    Budapest
  • ISSN
    1530-0889
  • Print_ISBN
    978-1-4673-6471-3
  • Type

    conf

  • DOI
    10.1109/DSN.2013.6575336
  • Filename
    6575336