DocumentCode
62826
Title
Address Translation for Throughput-Oriented Accelerators
Author
Pichai, Bharath ; Hsu, Lisa ; Bhattacharjee, Abhishek
Volume
35
Issue
3
fYear
2015
fDate
May-June 2015
Firstpage
102
Lastpage
113
Abstract
With processor vendors embracing hardware heterogeneity, providing low overhead hardware and software abstractions to support easy-to-use programming models is a critical problem. In this context, this work sets the foundation for designing memory management units (MMUs) for GPUs in CPU/GPU systems, the key mechanism necessary to support the increasingly important unified address space paradigm in heterogeneous systems.
Keywords
graphics processing units; microprocessor chips; storage management chips; CPU/GPU systems; MMU; address translation; hardware abstractions; hardware heterogeneity; heterogeneous systems; memory management units; processor vendors; programming models; software abstractions; throughput-oriented accelerators; unified address space paradigm; Benchmark testing; Graphics processing units; Hardware; Instruction sets; Memory management; Programming; cache-conscious wavefront scheduling; memory management unit; page table walk;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2015.44
Filename
7106386
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