Optimization of 3D stack for electrical and thermal integrity

Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.