Electrical and morphological characterization for high integrated silicon interposer and technology transfer from 200 mm to 300mm wafer

To achieve high density and high speed transmission between chips, a silicon interposer with copper (Cu) Through Silicon Vias (TSVs) technologies have been required. In previous papers, we reported process development and integration with 200mm wafer. It has been shown that high aspect ratio TSVs were filled with Cu without any voids. Delamination of dielectric layers did not occur on both side of silicon interposer. Furthermore electrical characterizations such as TSV kelvin resistance, daisy chain resistance between TSVs were reported [1][2]. In this paper, the first part reports morphological data for micro bumps. We focused on the characterization of Cu/Ni/Solder micro bumps after integrations of the silicon interposer process flow by Scanning Electron Microscope (SEM) cross section and Nano-Auger spectroscopy. The second part describes the electrical data for the silicon interposer. We focused on the fusion current tests and high frequency properties (RF test) of TSVs. The last part reports on the technology transfer from 200mm to 300mm wafer line in order to achieve low cost silicon interposers. Based on technical data from studies and process integration on 200mm line, processes are transferred to 300mm wafer line and first electrical and morphological characterizations are introduced.