A PoP structure to support I/O over 1000

PoP structure is widely used in mobile devices which memory package is directly attached to the top of the application processor. This structure, which has a smaller form factor and short interconnection distance between memory and processor chip. As the market demands more speed and bandwidth, the memory devices are moving from LPDDR to LPDDR3 and even wide I/O to support future requirements. Since wide I/O memory needs more than 1000 I/Os, the conventional PoP structure such as TMV with limited fine pitch capabilities up to 0.4 mm may not be able to support high I/O counts in the future. In this paper we propose a “Copper Pillar” structure in the peripheral area of the CSP package. For targeting 0.2 mm pitch copper pillars, 6 rows of interconnection on the peripheral of the bottom CSP package that can support 1224 I/Os. We have successfully making copper pillars with pitch as small as 0.2 mm and pillar height as high as 100 um. The PoP connection can be made through the solder ball on the bottom of the memory package to the copper pillar on top of processor substrate. In this paper, the process of making 0.2 mm pitch copper pillar will be discussed. And 0.2 mm PoP connection is demonstrated.