Innovative wafer-level encapsulation & underfill material for silicon interposer application

This paper is dedicated to the full integration of a new silicone-based material for Molding-Underfilling (MUF) on silicon interposer wafers containing Through Silicon Vias (TSVs) and top dice. The developments were carried out in the frame of “silicon package” where the silicon interposer is either reported on P-BGA or directly assembled on board. After a materials screening with regard to warpage issue, “molding last” was studied with the selected material, including compatibility with temporary bonding debonding, bumping, sawing and report on organic substrate. A focus is made on void-less molding-underfilling process development and wafer level reliability evaluation of first level (die to wafer) interconnections and TSV subjected to thermal cycles. For this study, a molding-last approach using a dry-film lamination process has been chosen. 170μm thick dice have been assembled on 120μm thin silicon interposers having 60μm diameter TSV via-last and encapsulated with optimized wafer-level MUF process. Electrical performances of the 35μm high Cu pillars interconnections have been measured on the interposer backside thanks to TSVs and rerouting. While the daisy chains resistances remained in specifications after molding and pre-conditioning, some electrical failures appeared after 250 thermal cycles. Cross-sections have highlighted cracks in solder joints leading to the development of an improved version of the compound. Finally, a complete test vehicle with a molded-underfilled interposer reported on an organic substrate has been achieved.