System level signal and power integrity analysis for 3200Mbps DDR4 interface

For single-ended signaling DDR4 channels at 3200Mbps, signal and power integrity issues become increasingly challenging with much smaller voltage and timing windows to balance the budget. As systems increase data rate and IO count, supply noise does not scale accordingly. We present a system level signal and power co-simulation analysis to optimize system performance under stringent timing requirement [1]. Signal integrity of DDR4 interface, such as inter-symbol interference ISI, reflection, and signal cross talk, needs to be minimized in order to meet an ever shrinking timing budget. Also, power delivery network (PDN) design becomes very difficult as a result of smaller die size and multilayer complex package design. SI and PI co-design optimization is driven by both channel performance and overall system cost.