System-level clock jitter modeling for DDR systems

As DDR speed continues to increase, uncorrelated timing jitter becomes a significant portion of channel timing budget. The dominant component of uncorrelated timing jitter comes from power supply noise induced jitter (PSIJ). DDR systems rely on tracking of this jitter between data and strobe signals. Due to inherent 90 degree offset between data and strobe signals, a significant amount of high-frequency jitter is not tracked and depending on the frequency content. In this paper, we analyze the impact of PSIJ for DDR4 systems running at 3.2Gb/s. We first present the jitter modeling methodology of PSIJ including jitter tracking mechanism. Then, we demonstrate the proposed modeling approach by applying to the design of the key DDR timing circuit blocks.