• DocumentCode
    628579
  • Title

    Size-free MEMS-IC high-efficient integration by using carrier wafer with self-assembled monolayer (SAM) fine pattern

  • Author

    Jian Lu ; Takagi, Hiroyuki ; Nakano, Yoshiaki ; Maeda, Ryutaro

  • Author_Institution
    Res. Center for Ubiquitous MEMS & Micro Eng. (UMEMSME), Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan
  • fYear
    2013
  • fDate
    28-31 May 2013
  • Firstpage
    1508
  • Lastpage
    1513
  • Abstract
    Wafer level integration of MEMS with IC will dramatically improve integration efficiency and reduce production cost. However, up to date, the large residual stress and the none-flat surface of MEMS processed wafers are still intractable problems. Besides, the expensive through-silicon vias (TSVs) process and the limitation of both die size and wafer size in wafer level integration are other difficult barriers that strictly restrict the flexibility of MEMS structure design and fabrication process. Therefore, a flexible approach by using self-assembled monolayer (SAM) coated carrier wafer was developed in our work for size-free MEMS and IC integration. First, MEMS and/or IC dies are self-aligned and temporarily bonded onto binding-sites, which was defined by hydrophobic-SAM (FDTS, CF3(CF2)7(CH2)2SiCl3) on carrier wafer. Then, those dies are simultaneously transferred to target IC processed wafer or interposer wafer by wafer level permanent bonding. The vapor phase deposited and lift-off patterned hydrophobic-SAM, FDTS, allows high speed self-align of MEMS and IC dies with various sizes and thicknesses onto binding-sites by surface tension of H2O with high accuracy (<;1μm). Carefully designed FDTS fine pattern was also proved effective to control the bonding strength (die shear strength <;0.01 kgf with controlling by FDTS; 3.5~4.0 kgf without FDTS fine pattern). It enables easy debonding of those dies from carrier wafer after permanent bonding step. An experimental prototype system was developed to investigate the process parameters, e.g. volume of H2O for self-assembly, wafer temperature for H2O evaporation, annealing process for bonding strength control, and etc. This simple and low cost approach offers unique merits of high flexibility in both geometries of the dies/wafers and processes of the devices with reasonably high efficiency when compared to C2- or C2W integration. This approach will be considerably valued for prototype development and low-medium volume production of MEMS-IC integrated systems, e.g. wireless sensor nodes.
  • Keywords
    annealing; hydrophobicity; integrated circuit design; internal stresses; micromechanical devices; monolayers; self-assembly; surface tension; three-dimensional integrated circuits; MEMS-IC high-efficient integration; MEMS-IC integrated systems; SAM fine pattern; TSV; annealing process; binding-sites; bonding strength; coated carrier wafer; die shear strength; evaporation; hydrophobic-SAM; interposer wafer; none-flat surface; residual stress; self-assembled monolayer; self-assembly; surface tension; through-silicon vias; vapor phase deposition; wafer level integration; wafer level permanent bonding; wireless sensor nodes; Accuracy; Bonding; Integrated circuits; Micromechanical devices; Plasma temperature; Temperature measurement; Water;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4799-0233-0
  • Type

    conf

  • DOI
    10.1109/ECTC.2013.6575771
  • Filename
    6575771