Layout parameter optimization based power and signal integrity performance improvement of high-speed interfaces of wirebond packages

The purpose of this paper is to present layout parameter optimization based power and signal integrity performance improvement investigation of high-speed interfaces in wirebond packages. Effects of different sections of signal nets, wirebond diameter, material and other stackup parameters on the noise performance of the package system is discussed in detail. The methodology developed in this paper, based on different sections of power and signal nets and supported by simulation results, provides design guidelines for the efficient and cost-effective wirebond IC-package systems development.