Electrochemically etched TSV for porous silicon interposer technologies

Silicon interposer technology offers System-In-Package (SiP) and System-On-Package (SoP) designers the unique possibility of achieving 3D integration without the need to implement Through-Silicon-Via (TSV) structures in active silicon, contributing to overall cost reduction of the final product. Silicon interposers require both horizontal and vertical interconnections, to redistribute the signals from the hosted chips. Vertical interconnections are achieved by TSV structures realized by Deep Reactive-Ion-Etching (DRIE) or LASER drilling processes. In this work is presented a lower cost alternative for realizing TSV on silicon wafers: electrochemical etching of silicon, forming vertical high aspect ratio macro-pores on the silicon wafer. The interposer itself is a macro-porous silicon layer, consisting of ordered, straight open pores at regular pitch. An optimized TSV fabrication process on low-cost (100)-oriented, p-type 10-20 Ωcm silicon wafers is presented. 100μm deep via with lateral diameter of 1.5μm and 2μm pitch have been achieved. In this work is reported the manufacture process, the achieved results.