A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Author

Noguchi, Hiroki ; Kushida, K. ; Ikegami, Kenshin ; Abe, Kiyohiko ; Kitagawa, Eiji ; Kashiwada, Shintaro ; Kamata, Chikayoshi ; Kawasumi, A. ; Hara, Hideki ; Fujita, S.

Author_Institution

Corp. R&D Center, Toshiba Corp., Kawasaki, Japan

fYear

2013

fDate

11-13 June 2013

Abstract

This paper presents a novel 1Mb STT-MRAM for power and area reduction of cache memory in micro-processors. This memory adopts current-integral sensing scheme for high speed read, and uses advanced perpendicular STT-MRAM for high speed write to achieve 250 MHz operation, 17.8 mW read power and 46.5 mW write power per 256-b I/O. Using a processor simulator, it has been confirmed the total cache power is reduced, whereas those for STT-MRAMs previously reported are increased compared with that for SRAM.

Keywords

MRAM devices; cache storage; magnetic tunnelling; microprocessor chips; active power; advanced perpendicular STT-MRAM; area reduction; cache memory; cache power; current-integral sensing scheme; high speed read; high speed write; microprocessors; nonvolatile magnetic caches; perpendicular MTJ based dual cell; power reduction; processor simulator; Cache memory; Computer architecture; Magnetic tunneling; Microprocessors; Nonvolatile memory; Random access memory; Sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2013 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Print_ISBN

978-1-4673-5226-0

Type

conf

Filename

6576612