3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation

3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t_m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for t_m=5 nm and isolation SiO₂ thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F²/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking t_m is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.